This disclosure relates generally to execution of instructions by a computer, and more specifically to execution of instructions in a transactional execution environment.
The number of central processing unit (CPU) cores on a chip and the number of CPU cores connected to a shared memory continues to grow significantly to support growing workload capacity demand. The increasing number of CPUs cooperating to process the same workloads puts a significant burden on software scalability; for example, shared queues or data-structures protected by traditional semaphores become hot spots and lead to sub-linear n-way scaling curves. Traditionally this has been countered by implementing finer-grained locking in software, and with lower latency/higher bandwidth interconnects in hardware. Implementing fine-grained locking to improve software scalability can be very complicated and error-prone, and at today's CPU frequencies, the latencies of hardware interconnects are limited by the physical dimension of the chips and systems, and by the speed of light.
Implementations of hardware Transactional Memory (HTM, or in this discussion, simply TM) have been introduced, wherein a group of instructions—called a transaction—operate in an atomic manner on a data structure in memory, as viewed by other central processing units (CPUs) and the I/O subsystem (atomic operation is also known as “block concurrent” or “serialized” in other literature). The transaction executes optimistically without obtaining a lock, but may need to abort and retry the transaction execution if an operation, of the executing transaction, on a memory location conflicts with another operation on the same memory location. Previously, software transactional memory implementations have been proposed to support software Transactional Memory (STM). However, hardware TM can provide improved performance aspects and ease of use over STM.
U.S. Patent Application Publication No. 2011/0029490 A1, titled “Automatic Checkpointing and Partial Rollback in Software Transaction Memory”, published Jul. 28, 2009, by Agarwal et al., incorporated herein by reference in its entirety, discloses carrying out write operations in a local data block while speculatively executing a given one of a plurality of transactions concurrently executing on a computer, and automatically creating an entry in a checkpoint log when reading from a shared memory. Additionally, it discloses continuously conflict checking during read and tentative commit operations, and carrying out a partial rollback upon detection of a conflict. The partial rollback is based upon the checkpoint log.
U.S. Patent Application Publication No. 2011/0321175 A1, titled “Monitoring and Reporting of Data Access Behavior of Authorized Database Users”, published Dec. 6, 2010, by Steve Slater, incorporated herein by reference in its entirety, discloses a computer-implemented system and method of monitoring data access activity of a user of a system. The method maintains a respective score for each of a plurality of monitored data access events, resulting in a set of scores for the user. The method continues by monitoring behavior of the user to detect occurrences of the monitored data access events, and updates the set of scores in response to detected occurrences of the monitored data access events. The method imitates an appropriate course of action when the updates set of scores is indicative of unauthorized, suspicious, or illegitimate data access activity.